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document:1g5-0115 rev.4 page 1 vis vs864648041b,vs1664648041b preliminary 8m,16mx64-bit sdram mod ule description the vs864648041b and vs1664648041b are 8m x 64 bit and 16m bit x 64 dual-in-line synchronous dram module (dimm). it consists of 8/16 cmos 8mx8 bit synchronous drams (vg36648041bt) with 4 banks and in standard 54 pin tsop-ii package. decoupling capacitors are mounted on power supply line for noise reduction. the module use serial presence detects implemented via a 2k-bit eeprom component. features vs864648041b, vs1664648041b : ? comply to intel pc100 specification ? single 3.3v () power supply ? utilizes -8h, -8l and -10 sdram components ? 8m x 64 bit (vs864648041b) and 16m x 64 bit (vs1664648041b) options ? fully synchronous with all signals referenced to a positive clock edge ? non-buffered ? programmable burst length (1,2,4,8 & full page) ? programmable wrap sequence (sequential/interleave) ? automatic precharge and controlled precharge ? auto refresh and self refresh modes ? i/o level : lvttl interface ? random column access in every cycle ? 4096 refresh cycles / 64ms ? serial presence detect (spd) with eeprom ? jedec standard pinout ? performance options (at 100mhz; units: clock) marking sdrams cl t rcd t rp t rc -8h -8h 2 2 2 7 -8l -8l 3 2 2 7 -10 -10 3 3 3 8 0.3v
document:1g5-0115 rev.4 page 2 vis vs864648041b,vs1664648041b preliminary 8m,16mx64-bit sdram mod ule pin configurations * 16m x 64 version only pin description pin name pin name pin name pin name pin name pin name pin name pin name 1 v ss 22 nc 43 v ss 64 v ss 85 v ss 106 nc 127 v ss 148 v ss 2 dq0 23 v ss 44 nc 65 dq21 86 dq32 107 v ss 128 cke0 149 dq53 3 dq1 24 nc 45 cs2 66 dq22 87 dq33 108 nc 129 * cs3 150 dq54 4 dq2 25 nc 46 dqmb2 67 dq23 88 dq34 109 nc 130 dqmb6 151 dq55 5 dq3 26 v dd 47 dqmb3 68 v ss 89 dq35 110 v dd 131 dqmb7 152 v ss 6 v dd 27 we 48 nc 69 dq24 90 v dd 111 cas 132 nc 153 dq56 7 dq4 28 dqmb0 49 v dd 70 dq25 91 dq36 112 dqmb4 133 v dd 154 dq57 8 dq5 29 dqmb1 50 nc 71 dq26 92 dq37 113 dqmb5 134 nc 155 dq58 9 dq6 30 cs0 51 nc 72 dq27 93 dq38 114 * cs1 135 nc 156 dq59 10 dq7 31 nc 52 nc 73 v dd 94 dq39 115 ras 136 nc 157 v dd 11 dq8 32 v ss 53 nc 74 dq28 95 dq40 116 v ss 137 nc 158 dq60 12 v ss 33 a0 54 v ss 75 dq29 96 v ss 117 a1 138 v ss 159 dq61 13 dq9 34 a2 55 dq16 76 dq30 97 dq41 118 a3 139 dq48 160 dq62 14 dq10 35 a4 56 dq17 77 dq31 98 dq42 119 a5 140 dq49 161 dq63 15 dq11 36 a6 57 dq18 78 v ss 99 dq43 120 a7 141 dq50 162 v ss 16 dq12 37 a8 58 dq19 79 clk2 100 dq44 121 a9 142 dq51 163 clk3 17 dq13 38 a10 59 v dd 80 nc 101 dq45 122 ba0 143 v dd 164 nc 18 v dd 39 ba1 60 dq20 81 wp 102 v dd 123 a11 144 dq52 165 sa0 19 dq14 40 v dd 61 nc 82 sda 103 dq46 124 v dd 145 nc 166 sa1 20 dq15 41 v dd 62 nc 83 scl 104 dq47 125 clk1 146 nc 167 sa2 21 nc 42 clk0 63 *cke1 84 v dd 105 nc 126 a12 147 nc 168 v dd pin name function pin name function a0 ~ a12 address input dqmb0 ~ dqmb7 dq mask enable dq0 ~ dq63 data-in/data - out clk0 ~ clk3 clock input ras row address strobe vdd power cas column address strobe vss ground we write enable sa0 ~ sa2 serial presence detect address ba0, ba1 bank address scl serial clock cke0, cke1 clock enable sda serial data i/o cs0 ~ cs3 chip select nc no connect v g 3 6 6 4 8 0 4 1 b t v g 3 6 6 4 8 0 4 1 b t v g 3 6 6 4 8 0 4 1 b t v g 3 6 6 4 8 0 4 1 b t v g 3 6 6 4 8 0 4 1 b t v g 3 6 6 4 8 0 4 1 b t v g 3 6 6 4 8 0 4 1 b t v g 3 6 6 4 8 0 4 1 b t 11 40 41 84 10 1 pin assignment (front view)
document:1g5-0115 rev.4 page 3 vis vs864648041b,vs1664648041b preliminary 8m,16mx64-bit sdram mod ule functional block diagram (8m x 64) cs0 dqmb0 dq0 dq1 dq2 dq4 dq5 dq6 dq7 dqm cs uo dqmb4 dq32 dq33 dq34 dq36 dq37 dq38 dq39 dqm cs u4 dq3 dq35 dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dqmb1 dq8 dq9 dq10 dq12 dq13 dq14 dq15 dqm cs u1 dqmb5 dq40 dq41 dq42 dq44 dq45 dq46 dq47 dqm cs u5 dq11 dq43 dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 cs2 dqmb2 dq16 dq17 dq18 dq20 dq21 dq22 dq23 dqm cs u2 dq19 dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dqmb3 dq24 dq25 dq26 dq28 dq29 dq30 dq32 dqm cs u3 dq27 dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dqmb6 dq48 dq49 dq50 dq52 dq53 dq54 dq55 dqm cs u6 dq51 dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dqmb7 dq56 dq57 dq58 dq60 dq61 dq62 dq63 dqm cs u7 dq59 dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 ras cas we cke0 a0 ~ a11 sdram u0 ~ u7 sdram u0 ~ u7 sdram u0 ~ u7 sdram u0 ~ u7 sdram u0 ~ u7 dqn 10 every dqpin of sdram v dd v ss to all sdrams a0 a1 a2 scl serial pd sa0 sa1 sa2 sda wp 47k w w 0.1f m 0.1f m sdram u0 ~ u7 ba0 & ba1 clk0 10 w clk2 10 w u0/u1/u4/u5 u2/u3/u6/u7
document:1g5-0115 rev.4 page 4 vis vs864648041b,vs1664648041b preliminary 8m,16mx64-bit sdram mod ule a0 a1 a2 scl serial pd sa0 sa1 sa2 sda wp cs0 dqmb0 dq0 dq1 dq2 dq4 dq5 dq6 dq7 dqm cs uo dqmb4 dq32 dq33 dq34 dq36 dq37 dq38 dq39 dqm cs u4 dq3 dq35 dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dqmb1 dq8 dq9 dq10 dq12 dq13 dq14 dq15 dqm cs u1 dqmb5 dq40 dq41 dq42 dq44 dq45 dq46 dq47 dqm cs u5 dq11 dq43 dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 cs2 dqmb2 dq16 dq17 dq18 dq20 dq21 dq22 dq23 dqm cs u2 dq19 dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dqmb3 dq24 dq25 dq26 dq28 dq29 dq30 dq31 dqm cs u3 dq27 dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dqmb6 dq48 dq49 dq50 dq52 dq53 dq54 dq55 dq51 dqmb7 dq56 dq57 dq58 dq60 dq61 dq62 dq63 dqm cs u7 dq59 dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dqm cs u8 dqm cs u12 dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dqm cs u9 dqm cs u13 dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dqm cs u10 dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dqm cs u11 dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dqm cs u14 dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 dqm cs u15 dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 cs3 ras cas we cke0 a0 ~ a11 sdram u0 ~ u15 sdram u0 ~ u15 sdram u0 ~ u15 sdram u0 ~ u15 sdram u0 ~ u15 dqn 10 every dqpin of sdram v dd v ss to all sdrams 10k cke1 v cc sdram u8 ~ u15 47k functional block diagram (16m x 64) w w cs1 0.1f m 0.1f m sdram u0 ~ u15 ba0 & ba1 dqm cs u6 dq0 dq1 dq2 dq4 dq5 dq6 dq7 dq3 clk0 10 w clk1 10 w clk2 10 w clk3 10 w u0/u1/u4/u5 u8/u9/u12/u13 u2/u3/u6/u7 u10/u11/u14/u15
document:1g5-0115 rev.4 page 5 vis vs864648041b,vs1664648041b preliminary 8m,16mx64-bit sdram mod ule command truth table function symbol cke cs ras cas we ba0 a10 a9 - a0 n - 1 n device deselect desl h x h x x x x x x no operation nop h x l h h h x x x mode rgister set mrs h x l l l l x x v bank activate act h x l l h h v v v read read h x l h l h v l v read with auto precharge reada h x l h l h v h v write writ h x l h l l v l v write with auto precharge writa h x l h l l v h v precharge select bank pre h x l l h l v l x precharge all banks pall h x l l h l x h x burst stop bst h x l h h l x x x
document:1g5-0115 rev.4 page 6 vis vs864648041b,vs1664648041b preliminary 8m,16mx64-bit sdram mo d ule absolute maximum ratings recommended dc operating conditions note 1. overshoot limit: v ih(max.) = v ddq + 2.0v with a pulse width < 3ns 2. undershoot limit: v il =v ssq - 2.0v with a pulse < 3ns and -1.5v with a pulse < 5ns capacitance ta = 25c,f = 1mhz parameter symbol value unit voltage on any pin relative to vss v in ,v out -1.0 to +4.6 v supply voltage relative to vss v dd ,v ddq -1.0 to +4.6 v short circuit output current i out 50 ma power dissipation p d 8mx64 8 w 16mx64 16 operating temperature t opt 0 to +70 j storage temperature t stg -55 to +125 j parameter symbol min typ max unit note supply voltage v dd 3.0 3.3 3.6 v input high voltage, all inputs v ih 2.0 - v dd + 0.3 v 1 input low voltage, all inputs v il -0.3 - 0.8 v 2 parameter symbol size typ max unit input capacitance (address, ras , cas , we bao, ba1) c11 8m x 64 16m x 64 - 50 85 pf input capacitance (cs0 ~ cs3) c12 8m x 64 16m x 64 - 25 25 pf input capacitance (cke0, cke1) c13 8m x 64 16m x 64 - 50 50 pf input capacitance (clk0~clk3) c14 8m x 64 16m x 64 - 25 25 pf input capacitance(dqmb0 ~ dqmb7) c15 8m x 64 16m x 64 - 15 22 pf data input/output capacitance(dq0 ~ dq63) c16 8m x 64 16m x 64 - 14 20 pf
document:1g5-0115 rev.4 page 7 vis vs864648041b,vs1664648041b preliminary 8m,16mx64-bit sdram mod ule dc characteristics(recommended operating conditions unless otherwise noted) notes 1. i cc depends on output loading and cycle rates. specified values are obtained with the output open. 2. i cc is measured on condition that addresses are changed only one time during t ck(min.) . parameter symbol test conditions vs864648041b -8h -8l -10 unit notes min max min max min max operating current i cc1 burst length = 1one bank active, io = 0ma (min ) cl = 3 720 720 630 ma 1,2 cl = 2 680 680 600 precharge standby current in power down mode i cc2 p il(max) , t ck = 10ns 24 24 24 ma i cc2 ps il(max) , t ck = 16 16 16 precharge standby current in nonpower down mode i cc2 n ih(min) , t ck = 10ns ih(min) input signals are changed one time during 2 clk cycles 200 200 200 ma i cc2 ns ih(min) , t ck = il(max) input signals are stable. 60 60 60 active standby current in power down mode i cc3 p il(max) , t ck = 10ns 45 45 45 ma i cc3 ps il(max) , t ck = 40 40 40 active standby current in nonpower down mode i cc3 n ih(max) , t ck = 10ns ih(min) input signals are changed one time during 2 clk cycles 200 200 200 ma i cc3 ns ih(min) t ck = il(max) input signals are stable. 100 100 100 operating current (burst mode) i cc4 (min) ,io = 0ma burst length = 4 cl = 3 1000 1000 800 ma 1,2 cl = 2 760 650 510 refresh current i cc5 (min) 1100 1100 960 ma 2 self refresh current i cc6 16 16 16 ma input leakage current (inputs) i li (max) pins not under test = 0v -40 40 -40 40 -40 40 ua iutput leakage current (i/o pins) i li (max) dq# in h - z, dout disabled -5 5 -5 5 -5 5 ua output low voltage v ol i ol = 2ma 0.4 0.4 0.4 v output high voltage v oh i oh = -2ma 2.4 2.4 2.4 v t rc t rc 3 ckev ckev ckev 3 csv 3 ckev 3 clkv ckev ckev ckev 3 csv 3 ckev 3 clev t ck t ck 3 t rc t rc 3 cke0.2v 0v in < v dd 0v out < v dd
document:1g5-0115 rev.4 page 8 vis vs864648041b,vs1664648041b preliminary 8m,16mx64-bit sdram mod ule dc characteristics(recommended operating conditions unless otherwise noted) notes 1. i cc depends on output loading and cycle rates. specified values are obtained with the output open. 2. i cc is measured on condition that addresses are changed only one time during t ck(min.) . parameter symbol test conditions vs1664648041b -8h -8l 10 unit notes min max min max min max operating current i cc1 burst length = 1one bank active, io = 0ma (min ) cl = 3 840 840 740 ma 1,2 cl = 2 800 800 700 precharge standby current in power down mode i cc2 p il(max) , t ck = 10ns 48 48 48 ma i cc2 ps il(max) , t ck = 32 32 32 precharge standby current in nonpower down mode i cc2 n ih(min) , t ck = 10ns ih(min) input signals are changed one time during 2 clk cycles 400 400 400 ma i cc2 ns ih(min) , t ck = il(max) input signals are stable 120 120 120 active standby current in power down mode i cc3 p il(max) ,t ck = 10ns 90 90 90 ma i cc3 ps il(max) , t ck = 80 80 80 active standby current in nonpower down mode i cc3 n il(max) , t ck = 10ns il(min) input signals are changed one time during 2 clk cycles 400 400 400 ma i cc3 ns ih(min) , t ck = il(max) input signals are stable 200 200 200 operating current (burst mode) i cc4 (min) ,io = 0ma burst length=4 cl = 3 1160 1160 930 ma 1,2 cl = 2 820 680 550 refresh current i cc5 (min) 2200 2200 1920 ma 2 self refresh current i cc6 32 32 32 ma input leakage current (inputs) i li (max) pins not under test = 0v -80 80 -80 80 -80 80 ua output leakage current (i/o pins) i lo (max) dq# in h - z., dout disabled -10 10 -10 10 -10 10 ua output low voltage v ol i ol = 2ma 0.4 0.4 0.4 v output high voltage v oh i oh = -2ma 2.4 2.4 2.4 v t rc t rc 3 ckev ckev ckev 3 csv 3 ckev 3 clkv ckev ckev ckev 3 csv 3 ckev 3 clev t ck t ck 3 t rc t rc 3 cke0.2v 0v in < v dd 0v out < v dd
document:1g5-0115 rev.4 page 9 vis vs864648041b,vs1664648041b preliminary 8m,16mx64-bit sdram mod ule a.c characteristics test conditions : (ta = 0 to 70c v dd = 3.3v, v ss = 0v) ac input levels(v ih /v il ) 2.0/0.8v input timing reference level/ output timing reference leveel 1.4v input and fall time 1ns output load condition 50pf parameter cas latency symbol vs864648041b/vs1664648041b unit -8h -8l -10 min max min max min max clk cycle time 3 t ck3 10 10 10 ns 2 t ck2 10 12 15 ns clk to valid output delay 3 t ac3 6 6 6 ns 2 t ac2 6 6 6 ns clk high pulse width t ch 3 3 3 ns clk low pulse width t cl 3 3 3 ns cke setup time t cks 2 2 3 ns cke hold time t ckh 1 1 1 ns address setup time t as 2 2 3 ns address hold time t ah 1 1 1 ns command setup time t cms 2 2 3 ns command hold time t cmh 1 1 1 ns data - in setup time t ds 2 2 3 ns data - in hold time t dh 1 1 1 ns output data hold time t oh 3 3 3 ns clk to output on low-z t lz 0 0 0 ns clk to output in hi-z 3 t hz 6 6 6 ns 2 6 6 6 row active to active delay t rrd 20 20 24 ns ras to cas delay t rcd 20 20 20 ns row precharge time t rp 20 20 30 ns row active time t ras 50 120k 50 120k 60 120k ns row cycle time t rc 70 70 90 ns last data in to burst stop t bdl 1 1 1 clk data-in to act (ref) command (auto precharge) t dal 1clk + t rp 1clk + t rp 1clk + t rp ns data-in to precharge t dpl 1 1 1 clk transition time t t 1 10 1 10 1 10 ns mode reg. set cycle t rsc 2 2 2 clk power down exit setup time t pde 2 2 3 ns self refresh exit time t srx 1 1 1 clk refresh time t ref 64 64 64 ms 0.3v
document:1g5-0115 rev.4 page 10 vis vs864648041b,vs1664648041b preliminary 8m,16mx64-bit sdram mod ule serial presence detect information vs864648041b (64mb version) byte function described function supported hex -8h -8l 10 -8h -8l 10 0 number of bytes used by vanguard 128bytes 80 1 total spd memory size 256bytes 08 2 memory type sdram 04 3 number of row addresses 12 0c 4 number of column addresses 9 09 5 number of banks on module 1row 01 6 module data width 64bits 40 7 module data width (continued) 0 00 8 module voltage interface lelevls lvttl 01 9 sdram cycle time. cas latency =3 10ns 10ns 10ns a0 a0 a0 10 sdram access from clock. cas latency =3 6ns 6ns 6ns 60 60 60 11 module configuration type non - parity 00 12 refresh rate/type 15.6us/self 80 13 sdram width, primary sdram x8 08 14 error checking sdram data width n/a 00 15 min. clock delay, back to back random column address 1 01 16 burst length supported 1,2,4,8 & page 8f 17 number of banks on each sdram device 4 04 18 cas latencies supported 2 & 3 06 19 cs latency 0 clk 01 20 write latency 0 clk 01 21 sdram module attributes non-buffered 00 22 sdram device attributes: general 0e 0e 23 sdram cycle time. cas latency =2 10ns 12ns 15ns a0 c0 e0 24 sdram access from clock. cas latency =2 6ns 6ns 6ns 60 60 60 27 min. row precharge time 20ns 20ns 30ns 14 14 1e 28 min. row active to row active 20ns 20ns 20ns 14 14 14 29 min. ras to cas delay 20ns 20ns 30ns 14 14 1e 30 min. ras pulse width 50ns 50ns 60ns 2e 2e 32 31 module bank density 64mb 10 32 command and address input setup time 2ns 2ns 3ns 20 20 30 33 command and address input hold time 1ns 1ns 1ns 10 10 10 34 data input setup time 2ns 2ns 3ns 20 20 30 35 data input hold time 1ns 1ns 1ns 10 10 10 62 spd data revision code rev.1.2 12 63 checksum for bytes 0-62 checksum data 01 21 79
document:1g5-0115 rev.4 page 11 vis vs864648041b,vs1664648041b preliminary 8m,16mx64-bit sdram mod ule byte function described function supported hex -8h -8l 10 -8h -8l 10 64 manufacturer ?s jedec id code continuation code 7f 65 manufacturer? s jedec id code vanguard 29 66-71 manufacturer? s jedec id code none ff 72 manufacturering location - - 73 manufacture?s part number v 56 74 manufacture?s part number s 53 75 manufacture?s part number 8 38 76 manufacture?s part number 6 36 77 manufacture?s part number 4 34 78 manufacture?s part number 6 36 79 manufacture?s part number 4 34 80 manufacture?s part number 8 38 81 manufacture?s part number 0 30 82 manufacture?s part number 4 34 83 manufacture?s part number 1 31 84 manufacture?s part number b 42 85 manufacture?s part number t 54 86 manufacture?s part number g (gold lead) s (tin lead) 47 53 87 manufacture?s part number a 41 88 manufacture?s part number ?-? 2d 89 manufacture?s part number 8 8 10 38 38 40 90 manufacture?s part number h l blank 48 4c 20 91 revision code for pcb a 41 92 revision code blank 20 93~94 manufacturering date year/week code - 95~98 module serial number serial number - 99~125 manufacturer specific data - - 126 module supports clock frequency 100mhz 64 127 intel specification details detail 100mhz information af ad ad 128~255 for customer use none ff
document:1g5-0115 rev.4 page 12 vis vs864648041b,vs1664648041b preliminary 8m,16mx64-bit sdram mod ule serial presence detect information vs1664648041b (128mb version) byte function described function supported hex -8h -8l 10 -8h -8l 10 0 number of bytes used by vanguard 128bytes 80 1 total spd memory size 256bytes 08 2 memory type sdram 04 3 number of row addresses 12 0c 4 number of column addresses 9 09 5 number of banks on module 2 row 02 6 module data width 64bits 40 7 module data width (continued) 0 00 8 module voltage interface lelevls lvttl 01 9 sdram cycle time. cas latency =3 10ns 10ns 10ns a0 a0 a0 10 sdram access from clock. cas latency =3 6ns 6ns 6ns 60 60 60 11 module configuration type non - parity 00 12 refresh rate/type 15.6us/self 80 13 sdram width, primary sdram x8 08 14 error checking sdram data width n/a 00 15 min. clock delay, back to back random column address 1 01 16 burst length supported 1,2,4,8 & page 8f 17 number of banks on each sdram device 4 04 18 cas latencies supported 2 & 3 06 19 cs latency 0 clk 01 20 write latency 0 clk 01 21 sdram module attributes non-buffered 00 22 sdram device attributes : general 0e 0e 23 sdram cycle time. cas latency =2 10ns 12ns 15ns a0 c0 e0 24 sdram access from clock. cas latency =2 6ns 6ns 6ns 60 60 60 27 min. row precharge time 20ns 20ns 30ns 14 14 1e 28 min. row active to row active 20ns 20ns 20ns 14 14 14 29 min. ras to cas delay 20ns 20ns 30ns 14 14 1e 30 min. ras pulse width 50ns 50ns 50ns 2e 2e 32 31 module bank density 64mb 10 32 command and address input setup time 2ns 2ns 3ns 20 20 30 33 command and address input hold time 1ns 1ns 1ns 10 10 10 34 data input setup time 2ns 2ns 3ns 20 20 30 35 data input hold time 1ns 1ns 1ns 10 10 10 62 spd data revision code rev.1.2 12 63 checksum for bytes 0-62 checksum data 02 12 80
document:1g5-0115 rev.4 page 13 vis vs864648041b,vs1664648041b preliminary 8m,16mx64-bit sdram mod ule byte function described function supported hex -8h -8l 10 -8h -8l 10 64 manufacturer ?s jedec id code continuation code 7f 65 manufacturer? s jedec id code vanguard 29 66-71 manufacturer? s jedec id code none ff 72 manufacturering location - - 73 manufacture?s part number v 56 74 manufacture?s part number s 53 75 manufacture?s part number 1 31 76 manufacture?s part number 6 36 77 manufacture?s part number 6 36 78 manufacture?s part number 4 34 79 manufacture?s part number 6 36 80 manufacture?s part number 4 34 81 manufacture?s part number 8 38 82 manufacture?s part number 0 30 83 manufacture?s part number 4 34 84 manufacture?s part number 1 31 85 manufacture?s part number b 42 86 manufacture?s part number t 54 87 manufacture?s part number g(gold lead s(tin lead) 47 53 88 manufacture?s part number a 41 89 manufacture?s part number 8 8 10 38 38 40 90 manufacture?s part number h l blank 48 4c 20 91 revision code for pcb a 41 92 revision code blank 20 93~94 manufacturering date year/week code - 95~98 module serial number serial number - 99~125 manufacturer specific data - - 126 module supports clock frequency 100mhz 64 127 intel specification details detail 100mhz information ff fd fd 128~255 for customer use none ff
document:1g5-0115 rev.4 page 14 vis vs864648041b,vs1664648041b preliminary 8m,16mx64-bit sdram mod ule 168 pin dimm mechanical dimension(front side) units : mm tolerances : 0.13 unless otherwise specified detail a detail b detail c golder plating lead pcb model no.s808b the use device is 8mx8 sdram, tsop sdram part no: vg36648041bt
document:1g5-0115 rev.4 page 15 vis vs864648041b,vs1664648041b preliminary 8m,16mx64-bit sdram mod ule ordering information 1 2 3 4 5 6 7 8 9 10 v x x xx xxxxxx x x x x x -x v : vis product 1 : ram family s : sdram dimm (168pin) 2 : memory density (work) 8 : 8m 16 : 16m 3 : i/o width 32 : x 32 64 : x 64 4 : operation mode and refresh with different density 648041 : 4k ref, 8mx8 sdram 5 : component revision blank : none a : a revision b : b revision 6 : component package t : tsop 7 : pc board finger plating g : gold s : tin/lead 8 : pc board revision blank : none a : a revision 9 : customer specific blank : none 10 : module speed -8h : 100mhz, cl = 2, trp=2, trcd = 2 -8l : 100mhz, cl = 3, trp=2, trcd = 2 -10 : 100mhz, cl = 3, trp=3, trcd = 3

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